Full chip integration tasks in SoCs commonly include integration of a digital part, an analog part, a power intent, and software (SW). All these parts are commonly performed in simulation. Therefore, simulation engines that test SoCs in mixed signal environments typically result in multiple, large signal output waveforms that are difficult to handle adequately and expediently for analysis. Accordingly, different data compression schemes have been used to reduce the size of signal waveforms stored in a database, with varying degrees of success. A problem that typically arises in this scenario is that highly compressed waveforms include multiple metadata references that increase the read time of the waveforms for de-compression (e.g., for post-simulation analysis). Furthermore, aggressive compression techniques may result in data loss for areas of a dataset that involve high resolution and high frequency signals (e.g., analog components of multiple waveforms).
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